1. Field of the Invention
The present invention relates to a numerically controlled oscillator circuit capable of numerically controlling an oscillation frequency. Oscillation frequency of the numerically controlled oscillator circuit is determined by an externally supplied digital value and is used in, for example, a frequency synthesizer, etc.
2. Description of the Related Art
A well known example of the conventional numerically controlled oscillator circuit is one disclosed in FIG. 6 of Japanese Patent Application Laid-open No. H1-114122 as a prior art of the invention disclosed thereby and has been utilized practically. A circuit construction of the prior art example is shown in FIG. 1. In FIG. 1, the conventional numerically controlled oscillator circuit is constructed with an accumulator 40, a read-only memory (ROM) 43 and a digital-to-analog (D/A) converter 44. The accumulator 40 is constructed with a Q-bit adder 41 and a Q-bit shift register 42 for holding a result of the addition from the Q-bit adder 41. A setting value represented by Q bits is externally supplied to an input terminal 101 of the accumulator 40 and a system clock having frequency f.sub.m is input to an input terminal 103 thereof to control a latching operation of the Q-bit shift register 42, that is, a latching operation of the accumulator 40. Therefore, when a constant value K is input to the input terminal 101 of the accumulator 40, an output of the accumulator 40 is increased by the constant value K every time period of 1/f.sub.m. The Q-bit adder 42 operates on modulo 2.sup.Q to return the output of the accumulator 40 to 0 every 2.sup.Q. Therefore, an output waveform of the Q-bit adder 42 is sawtooth. The ROM 43 stores, for example, a digital value of sin(2.pi.A/2.sup.Q) in an address A thereof. Since the output of the accumulator 40 gives a phase of a sine wave and 2.pi. radian corresponds to the digital value 2.sup.Q, an output of the ROM 43 becomes a train of numerical values indicative of a sine wave having a constant frequency. The train of the numerical values output from the ROM 43 is converted into an analog signal by the D/A converter 44, resulting in a sine wave signal at the output terminal 102. The system clock at the input terminal 103 of the accumulator 40 is also supplied to the D/A converter 44 to provide a timing for executing a D/A conversion. A frequency f.sub.0 of the output of the D/A converter 44 is given by f.sub.0 =f.sub.m .times.K/2.sup.Q. That is, the oscillator circuit shown in FIG. 1 is numerically controlled to oscillate at a frequency which is determined by the setting value K which is an externally supplied digital value.
FIG. 2 shows a construction of another conventional numerically controlled oscillator circuit. This construction corresponds to one shown in FIG. 1 of the aforementioned Japanese Patent Application Laid-open No. H1-114122. The oscillator circuit shown in FIG. 2 comprises an accumulator 40, a Q-bit register 45, a D/A converter 44, a voltage-controlled oscillator (VCO) 46 and a frequency divider (1/D) 47. The accumulator 40 is constructed with a Q-bit adder 41 and a Q-bit shift register 42. An operation of the accumulator 40 is similar to that of the accumulator shown in FIG. 1. The Q-bit register 45 performs a latching operation according to a clock obtained by an output clock of the VCO 46 divided by D by the frequency divider 47. Assuming that the oscillation frequency of the VCO 46 is constant and the Q-bit register 45 latches a sawtooth wave from the accumulator 40 always in same phases, the D/A converter 44 outputs a DC signal. Since this state corresponds to the state in which the oscillation frequency of the VCO 46 is constant, the system is in a stable state. On the other hand, if Q-bit register 45 latches the sawtooth wave from the accumulator 40 every time in slightly different phases, the output of the D/A converter 44 does not become a DC signal, so that the oscillation frequency of the VCO 46 shall be varied. As described in the aforementioned Japanese Patent Application Laid-open No. H1-114122 in detail, if the oscillation frequency of the VCO 46 varies in a direction in which the variation of phase for latching the output of the accumulator 40 by the Q-bit register 45 is restricted, the system ultimately becomes stable due to the principle of negative feedback and the oscillation frequency of the VCO 46 ultimately becomes constant. The frequency f.sub.0 at an output terminal 102 is given by f.sub.0 =D.times.f.sub.m .times.K/2.sup.Q, where f.sub.m is a system clock frequency and K is a setting value input to an input terminal 101. In the circuit shown in FIG. 2, since the ROM for storing the sine wave data is unnecessary and the D/A converter 44 operates at a frequency which is 1/D of the oscillation frequency of the VCO 46, the oscillator circuit can operate at high frequency relatively easily.
In the oscillator circuit shown in FIG. 1, however, there is a problem that it is difficult to obtain a high frequency as the output thereof. That is, in order that the D/A converter 44 outputs a sine wave having frequency f.sub.0, the clock frequency f at which the ROM 43 and the D/A converter 44 operate must be 2 times the oscillation frequency f.sub.0 or more according to the known sampling theorem. Practically, however, in order to restrict high harmonic components of the output sine wave small enough, the clock frequency f.sub.m is preferably 5 times the oscillation frequency f.sub.0 or more. Therefore, in order to obtain the oscillation frequency f.sub.0 in the order of, for example, 50 MHz, the clock frequency f.sub.m is in a range from 100 MHz to 250 MHz or more. It is, however, very difficult to operate the D/A converter 44 at such high frequency and, even if a D/A converter 44 operable at such high frequency be realized, the D/A converter 44 has to be very expensive. Further, when the clock frequency f.sub.m is in a range from 100 MHz to 250 MHz, an access time to the ROM 43, which is also defined by the clock frequency f.sub.m, becomes in a range from 4 ns to 10 ns which is very difficult to realize even if expensive ultra high speed memory elements are used.
On the other hand, the circuit shown in FIG. 2 does not require the ROM 43 and the operating frequency of the D/A converter 44 thereof is relatively low, and, therefore, it is possible to obtain a high oscillation frequency compared with the circuit shown in FIG. 1. However, in order to obtain high oscillation frequency, the D/A converter 44 of the oscillator circuit shown in FIG. 2 must be expensive. As mentioned above, the oscillation frequency of the VCO 46 is stabilized by the principle of negative feedback and phase noise is included in the output of the VCO 46 when the frequency dividing ratio D is large. In view of this, the frequency dividing ratio D is preferably 20 or less. In such case, when the oscillation frequency is 50 MHz, the operating frequency of the D/A converter 44 must be about 2.5 MHz. However, a D/A converter 44 operable at 2.5 MHz is not inexpensive but rather relatively expensive. In this sense, the oscillator circuit shown in FIG. 2 is not suitable in obtaining a high frequency output.
Since both of the oscillator circuits shown in FIGS. 1 and 2 require the D/A converter 44, it is difficult to fabricate it as a digital LSI. That is, when the oscillator circuit is made as an LSI, the LSI includes digital circuit portions and analog circuit portions and it is very difficult to fabricate such an LSI using an inexpensive gate array.
An object of the present invention is to provide a numerically controlled oscillator circuit which does not require an expensive D/A converter, is easily capable of obtaining high frequency output easily and can be fabricated in an LSI.